METHOD OF MINIMIZING BOOLEAN FUNCTIONS FOR DESIGNING DIGITAL COMBINATIONAL CIRCUITS
نویسندگان
چکیده
The article discusses a two-stage method of minimizing Boolean functions for designing digital combinational circuits. At the first stage, search simple conjuncterms is carried out by bitwise division set initial conjuncterms. this way tautology does not appear, low-rank are found without intermediate gluing. second minimal performed chain coverage table In cyclic part, fragments found, which quite simple. To reduce computational load at branching points chains, decision can be made about entering or removing corresponding conjuncterm from finite based on calculation complexity factor in vicinity branching. proposed heuristic.
منابع مشابه
Combinatorial method for Boolean SAC functions designing
In this paper a new approach for designing Boolean functions that satisfy the Strict Avalanche Criterion (SAC) is presented. The advantage of the suggested approach is the simplicity of its realization and the significant greater number of the generated functions compared to the known methods. The formalized procedure for construction of nonbalanced and balanced SAC-functions is described in de...
متن کاملAlgorithms for Solving Boolean Satisfiability in Combinational Circuits
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover, Boolean Satisfiability is in the core of algorithms for solving Binate Covering Problems. This paper describes how Boolean Satisfiability ...
متن کاملA Fault Detection Method for Combinational Circuits
As transistors become increasingly smaller and faster and noise margins become tighter, circuits and chip specially microprocessors tend to become more vulnerable to permanent and transient hardware faults. Most microprocessor designers focus on protecting memory elements among other parts of microprocessors against hardware faults through adding redundant error-correcting bits such as parity b...
متن کاملDigital Combinational Circuits Design By QCA Gates
Different logic gates like MV, NOT, AOI, NNI etc under QCA nanotechnology are introduced. NNI gate is highly effective regarding space and speed consideration. Any Boolean functions are synthesized by MV and NNI gates or simply NNI gates alone, eliminating inverter (NOT) gate. A new method for realizing adder circuit in binary reversible logic is invented. This procedure synthesizes for a more ...
متن کاملMinimizing Power Dissipation in Combinational Circuits During Test Application
Yield, Reliability and Power Supply considerations motivate the need to minimize power dissipation during test application. Two techniques for minimizing power dissipation when tests are applied to static CMOS combinational circuits are proposed. They are: (i) Test set ordering; and (ii) Repetition of test vectors. We show that: although (i) is NP-Hard good heuristics can be developed; and an o...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: Ìnfokomunìkacìjnì tehnologìï ta elektronna ìnženerìâ
سال: 2023
ISSN: ['2786-4553']
DOI: https://doi.org/10.23939/ictee2023.01.146